1. Field of the Invention
The present invention relates to an output circuit device, in particular to an output circuit device which can realize stabilization of the output potential and the supply potential.
2. Description of the Prior Art
In the recent semiconductor devices, the degree of integration and the density have been increased for the purpose of reducing the chip size, and also there is a trend toward increasing the speed of operation to improve the processing capability.
As a method of increasing the degree of integration and the density, one may mention the method of decreasing the width of the wiring that is formed of alminum or the like to reduce the area occupied by the wiring in comparison to the area of the chip. However, when the width of the wiring is decreased, it leads to an increase in the inductive load of the wiring, namely, in the inductance.
On the other hand, as a method of increasing the speed, one may mention the method of increasing the size of the transistor in order to enhance the current driving capability. However, an increase in the transistor size will result in a reduction in its on-resistance.
As understood from the above discussion, by decreasing the wiring width and increasing the transistor size, there used to be generated problems that are caused by an increase in the inductive load and a reduction in the on-resistance. Referring to a prior example as shown in FIGS. 1(A)* and 1(B)*, these problems will be described next.
FIG. 1(A) illustrates an example of a configuration of a general inverter circuit that takes into account the inductance components of a power source wiring and of the output wiring. The inverter circuit is composed of a P-channel MOS transistor (referred to as the "PMOS" hereinafter) 1 and an N-channel MOS transistor (referred to as the "NMOS" hereinafter) 3. The source terminal of the PMOS 1 is connected to a high level voltage source V.sub.DD that supplies a potential V.sub.DD via an inductance 5 of the power source wiring made of aluminum, and the source terminal of the NMOS 3 is connected to a low level voltage source V.sub.SS that supplies a potential V.sub.SS (ordinarily O V) via an inductance 7 of the power source wiring made of aluminum. Further, the gate terminals of both of the PMOS 1 and the NMOS 3 are connected to an input terminal IN to which is input a signal to be inverted, and the respective drain terminals are connected to an output terminal OUT via an inductance 9 of the output wiring formed of aluminum. In addition, a load capacity 11 is connected to the output terminal OUT.
Now, when a signal of low level state (potential V.sub.1) is input to the input terminal IN, the PMOS 1 is brought to the conducting state and the NMOS 3 is brought to the nonconducting state. Consequently, a current flows in the load capacity 11 via the PMOSZ 1 from the high level voltage source V.sub.DD, bringing the output terminal OUT to a high level state (potential V.sub.DD). Further, when a signal of high level state (potential V.sub.2) is input to the input terminal IN, the PMOS 1 is brought to the nonconducting state and the NMOS 3 is brought to the conducting state. Then , the charges that are accumulated in the load capacity 11 flow into the low level voltage source V.sub.SS via the NMOS 3, bringing the output terminal OUT to the low level state (potential V.sub.SS). Therefore, by the action explained above, a signal which is the inversion of the signal that is input to the input terminal is output from the output terminal OUT.
Now, in an inverter circuit of such a configuration, when the current driving capability is enhanced by increasing the transistor size in order to invert the output potential at high speed, the on-resistance of the transistor is descreased. Then, between the high level voltage source V.sub.DD and the load capacity 11, and the low level voltage source V.sub.SS and the load capacity 11, there is formed a resonance circuit that consists of the inductance components of the power source wiring and the output wiring, the load capacity, and the on-resistance.
Because of this, the input potential is inverted from potential V.sub.SS to potential V.sub.DD as shown in FIG. 1(B), bringing the NMOS 3 to the conducting state. Then, the charges that are accumulated in the load capacity 11 flow rapidly into the low level voltage source V.sub.SS, reducing the output voltage from potential V.sub.DD to potential V.sub.SS. This generates the flow of a transient current in the vicinity of potential V.sub.SS, causing the so-called undershoot phenomenon. In addition, also because of the ease of rise in the output potential from potential V.sub.SS potential V.sub.DD due to a rapid charging of the load capacity 11 by the influx of the current from the high level voltage source V.sub.DD, a transient current flows in the vicinity of potential V.sub.DD causing the so-called overshoot phenomenon.
As a result, the output potential 11 fluctuates temporarily immediately after its inversion, and leads to the generation of a problem in which an erroneous signal for potential is transmitted. Further, there will be induced fluctuations in the potentials of the high level voltage source V.sub.DD and the low level voltage source V.sub.SS, by which the input and output levels of other elements that are connected to the respective power source wirings are fluctuated also, giving rise to a fear of causing a malfunction of the circuit.